`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:33:19 03/31/2014 
// Design Name: 
// Module Name:    user_control 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module user_control(clk, clk_key, data_key, rst, status
    );
	input clk, clk_key, rst, data_key;
	//output [7:0] led;
	output reg [5:0] status;//[0]bullet, [2:1] direction
	
 
   wire data;
	wire [7:0] key, key_out;
	wire start1_u;
	wire [1:0] start1_dir;
	wire start2_u;
	wire [1:0] start2_dir;




	keyboard keyboard(clk_key, data_key, key, start1_dir, start1_u);
	keyboard_2 keybo2(clk_key, data_key, key, start2_dir, start2_u);
	

	
	always@(*)
	begin
	   status[0] <= start1_u;
		status[1] <= start1_dir[0];//left
		status[2] <= start1_dir[1];//right
		status[3] <= start2_u;
		status[4] <= start2_dir[0];//left
		status[5] <= start2_dir[1];//right
	end
	
	wire [2:0] data_in;
	assign data_in = status;
	
endmodule
